Team Members: Ginat Weisberg, Noa Vaknin

Supervisors / Mentors: Prof. Freddy Gabbay, Alex Grinshpun, Sarit Shvimmer

 

Transistor aging poses a fundamental challenge to the long-term reliability of integrated circuits. Of particular concern is asymmetric aging, where non-uniform degradation across circuit elements leads to critical timing violations and ultimately, functional failure. This phenomenon is primarily attributed to Bias-Temperature Instability (BTI), which induces a threshold voltage shift and reduced carrier mobility, directly impacting circuit speed and stability.

In our project, we developed and validated novel anti-aging solutions to combat the effects of asymmetric transistor degradation. We implemented anti-aging techniques on a RISC-V processor architecture within an FPGA environment. By accelerating the aging process of the chip to test the anti-aging solutions, we demonstrate effective mitigation of the asymmetric aging. Our solutions aim to prevent prolonged static stress on specific components by activating redistribution of stress among transistors. Our technique is designed to homogenize degradation profiles, which is vital for ensuring the long-term performance and robustness of future high-performance integrated circuits.