Members: Idan Yamin, Shelley Aviran-Hartal

Supervisor: Intel - Ori Yefet, University - Dr. Shimon Mizrahi

In complex memory data structures, synchronizing read and write clocks is crucial for maintaining data flow and system efficiency. Our chip design efforts focus on optimizing space and maximizing effectiveness. We are developing a sophisticated memory unit with internally synchronized shared linked lists to streamline reading and writing processes, eliminating the need for external units and conserving storage space and chip frequency. Our project aims to create a complex unit for reading and writing to memory modules while improving chip frequency and space utilization. We plan to design and verify a synchronized shared linked list unit.

Our methods include:

1. Implement advanced techniques such as formal verification and digital verification to ensure the design's correctness and functionality.
2. Enhancing Design Frequency and Area Efficiency: Optimize the design to achieve higher operating frequencies without compromising functionality or reliability.
3. On-Chip Connectivity Testing: Perform comprehensive on-chip connectivity tests to ensure seamless integration and communication with other complex designs on the chip.

Our results: We have progressed from the initial gate-level design to more comprehensive stages, emphasizing System Verilog design and verification. The design incorporates a pointer memory unit, a data memory unit, and multiple arbiters to handle complex memory read and write operations. We completed the full design process, including a specified block diagram, a micro-architecture specification document, System Verilog design, and formal verification.