Members: Tal Amit

Supervisor: Nir Geron - head of Bluetooth team - Intel, Dr. Shimon Mizrahi

The performance of the sub-units in Intel's Bluetooth chip has a substantial effect on the chip's overall performance. One of the main performance aspects is the chip's throughput. This project aims to enhance overall performance by shortening the communication latency between two components on the chip (the D-unit and the memory unit) and improving the throughput, specifically by reducing the latency between a D-UNIT reading request and the receipt of the read data from memory. This is achieved by leveraging our understanding of the D-UNIT and MEMORY-UNIT behavior to anticipate the next reading request. By sending the request to the memory unit preemptively, we ensure the data is ready for the D-UNIT when it makes the request. Furthermore, a secondary requirement for this project was to add a second D-unit that communicates with the same memory unit. The primary challenge was to integrate an additional unit, which inherently slows down memory communication, while simultaneously developing a prediction mechanism that ultimately enhances the overall throughput. To execute the project, sub-units were built: a prediction unit, which contains a small local FIFO memory, and an arbitration unit that manages memory access. The results of the block verification indicate that, with the prediction bridge, we achieved a 50 to 70 percent improvement in D-unit to memory communication throughput, depending on the block's operating mode.