Team Members: Itay Yonatanov, Ido Parchomovsky

Supervisors / Mentors: Prof. Freddy Gabbay

 

As semiconductor technologies advance, chip designs become increasingly complex and more sensitive to reliability effects. One of the critical reliability concerns in modern semiconductors is dynamic IR (or voltage) drop, across the Power Delivery Network of the chip. Excessive voltage drop slows down transistors and may impact the circuit timing resulting in circuit failure.

Dynamic IR drop is caused by rapid changes in current demand due to transistor switching activity. It arises from both resistive effects and, more significantly, inductive effects in the power grid.

The goal of our project was to detect dynamic IR drop in early stages of the chip design process.

This has been done by executing synthesis and place and route to create a physical implementation of a RISC-V processor, and creating a large dataset of dynamic IR Drop feature maps. These feature maps were used to train our machine learning module.

The machine learning module is trained to predict where the most severe voltage drop will occur in a specific area of the electrical chip.