Members: Roy Toledano

Supervisor: Amitai Uliel, Yigal Dahan, Dr. Shimon Mizrahi

In the realm of hardware design, particularly front-end design, hardware memory presents a unique challenge: configurations are fixed prior to fabrication, necessitating all adjustments to be finalized before production. The last opportunity for modifications arises during post-silicon validation, where critical changes can be implemented based on the initial silicon feedback.

This project, titled ""Hardware Configurable Memory,"" addresses the intricacies of data transfer across the chip. Typically, hardware designs are based on architectural assumptions; however, real-life traffic patterns can significantly deviate from these assumptions. This discrepancy can lead to inefficient memory allocation and suboptimal performance.

The core problem addressed by this project is the need to dynamically adjust memory size based on actual traffic requirements observed during post-silicon validation. By monitoring real-life traffic, the project aims to provide a solution that allows for the reconfiguration of memory allocation post-fabrication. This approach enables the system to adapt to varying traffic conditions, ensuring optimal memory usage.

The result of this research is a design capable of receiving software inputs post-silicon to modify the memory allocated to different traffic types. This innovative solution not only enhances system performance by tailoring memory resources to real-time needs but also conserves valuable chip space by minimizing the allocation of excess memory reserved for potential but unneeded usage scenarios.